The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, as a critical dimension (CD) shrinks accompanying increasing IC complexities for more integrated functionality, it is ever more risky financially to manufacture semiconductor devices at advanced nodes. Thus, it is important that early warnings be enabled to detect hot spots of potential faults like openings or bridges in the printed patterns of geometric layouts on wafers. A design for manufacturability (DFM) simulation is design for a software tools for this early detection of potential faults during the design stage. Accuracy of the DFM simulation is critical to ensure the prediction results for early warnings to have meaningful impacts. Accordingly, what are needed are a method and a system to improve the DFM simulation.